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Título: IMPLEMENTATION OF CODEC GOLAY-24 FOR FPGA
Autor(es): LEANDRO PEREIRA DE LIMA E SILVA
Colaborador(es): MARCO ANTONIO GRIVET MATTOSO MAIA - Orientador
Catalogação: 05/JUL/2012 Língua(s): PORTUGUESE - BRAZIL
Tipo: TEXT Subtipo: SENIOR PROJECT
Notas: [pt] Todos os dados constantes dos documentos são de inteira responsabilidade de seus autores. Os dados utilizados nas descrições dos documentos estão em conformidade com os sistemas da administração da PUC-Rio.
[en] All data contained in the documents are the sole responsibility of the authors. The data used in the descriptions of the documents are in conformity with the systems of the administration of PUC-Rio.
Referência(s): [pt] https://www.maxwell.vrac.puc-rio.br/projetosEspeciais/TFCs/consultas/conteudo.php?strSecao=resultado&nrSeq=19818@1
[en] https://www.maxwell.vrac.puc-rio.br/projetosEspeciais/TFCs/consultas/conteudo.php?strSecao=resultado&nrSeq=19818@2
DOI: https://doi.org/10.17771/PUCRio.acad.19818
Resumo:
Error-correcting codes are fundamental pieces of modern telecommunications systems. Through their usage, data can be transmitted through noisy channel without noise-induced errors making the whole transmission unviable. In digital systems, these codes are composed by a set of bits associated with the transmitted data, and sent right along with them. These bits contain mathematical properties which allow given a limited number of wrong received bits, detect and, in some cases, correct these errors. When embedded in FPGAs (field-programmable gate arrays), a single integrated circuit can contain the necessary logic to encode and/or decode messages with error-correcting codes as also include other logic pertinent to the desired application. In this work, we develop an encoder and a decoder for the extended binary Golay code in VHDL for FPGA implementation.
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