Low power supply consumption hás become one of the main issue in eletronic industry for many product áreas such as cellular telephones, portable personal computers and biomedical implants. The aim of this work is to investigate the main drawbacks involved in the design of CMOS analog cells biased in weak inversion. Biasing a cell in weak inversion makes it possible to archieve a power consumption that is one thousandth lower than common analog cells designed to operate in strong inversion. This work has involved the following subject: a study of models for MOS transistors operating in weak inversion and strong inversion regions; a methodology to convert LEVEL 2 Spice model to EKV model; study of basic analog cell blocks suitable to low power mixed mode IC design; design methodology for low power analog cells; comparison between these cells and some commercial ones; study of analog layout techniques. Firstly, this work reviews the state-of-art of analog cell design including MOS transistor operation and modeling in the weak inversion region. Secondly we discuss the operation of some basic structures, such as current mirors and differential amplifiers, biased in weak inversion. This study helped us to understand the benefits and drawbacks involved in working with MOS transistors biased in this region. Next we describe a methodology to convert process parameters suppied by the foundries, usually LEVEL 2 Spice model, to the EKV model that was developed by EPFL (Swiss Federal Institute of Technology - Lausanne). Since EKV model is continuous in all regions, we expect to archieve better agreement between simulation results and manufacturing results. In order to test and validate the design methodology we chose to develop first a set of cells for this foundry comforming to a foundry with expertise in low voltage analog cell design. These tests were carried ou through standardized hierarchical simulation files in order to decrease the total number of simulatiom files required. Finally, we present some techniques for the layout of analog cells that improve circuit sensibility to transistor mismatching and process variation. The work shows us that it is feasible to design low power analog circuit using MOS transistors operating in weak inversion region. The methodology was even able to synthesize cells that are similar in performance to commercial ones. Therefore, it is possible to develop a çow power analog cell library which is suitable to designing application specific integrated circuits.